EPM7064STC44-10N

PLD, usable gate, ISP, pin-to-pin delay

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PartNumber:: EPM7064STC44-10N

Brand:: Altera Corporation - ALTR | Pack: QFP | D/C: 09+

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Products Upload time: 2011-03-10

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Part Number:EPM7064STC44-10N
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Product Summary

The EPM7064STC44-10N is a high-density, high-performance PLD based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064STC44-10N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. It complies with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

Absolute maximum ratings:(1)VCC, Supply voltage With respect to ground: –2.0v min, 7.0 V max; (2)VI, DC input voltage With respect to ground: –2.0v min, 7.0 V max; (3)IOUT, DC output current, per pin: –25mA min, 25 mA max; (4)TSTG, Storage temperature: –65 to 150 ° C at No bias ; (5)TAMB, Ambient temperature Under bias: –65 to135 ° C; (6)TJ, Junction temperature:150 ° C max at Ceramic packages, under bias ; (7)TJ, Junction temperature:135 ° C max at PQFP and RQFP packages, under bias 135 ° C.

Features

Features:(1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices: ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.