ATF1508ASL-20AC100

Product Summary

The ATF1508ASL-20AC100 is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508ASL-20AC100’s enhanced routing switchmatrices increase usable gate count and increase odds of successful pin-locked design modifications. The ATF1508ASL-20AC100 has up to 96 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable.

Parametrics

ATF1508ASL-20AC100 absolute maximum ratings: (1)Temperature Under Bias: -40℃ to +85℃; (2)Storage Temperature: -65℃ to +150℃; (3)Voltage on Any Pin with Respect to Ground: -2.0V to +7.0V; (4)Voltage on Input Pins with Respect to Ground During ProgrammingL: -2.0V to +14.0V; (5)Programming Voltage with Respect to Ground: -2.0V to +14.0V.

Features

ATF1508ASL-20AC100 features: (1)High-density, High-performance, Electrically-erasable Complex; (2)Programmable Logic Device, 128 Macrocells; 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell; 84, 100, 160 Pins; 7.5 ns Maximum Pin-to-pin Delay; Registered Operation up to 125 MHz; Enhanced Routing Resources; (3)Flexible Logic Macrocell, D/T/Latch Configured Flip-flops; Global and Individual Register Control Signals; Global and Individual Output Enable; Programmable Output Slew Rate; Programmable Output Open Collector Option; Maximum Logic Utilization by Burying a Register within a COM Output; (4)Advanced Power Management Features, Automatic 10 μA Standby for “L” Version; Pin-controlled 1 mA Standby Mode; Programmable Pin-keeper Inputs and I/Os; Reduced-power Feature per Macrocell; (5)Available in Commercial and Industrial Temperature Ranges; (6)Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages; (7)Advanced EE Technology, 100% Tested; Completely Reprogrammable; 10,000 Program/Erase Cycles; 20-year Data Retention; 2000V ESD Protection; 200 mA Latch-up Immunity; (8)JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported; (9)Fast In-System Programmability (ISP) via JTAG; (10)PCI-compliant; (11)3.3 or 5.0V I/O Pins; (12)Security Fuse Feature; (13)Green (Pb/Halide-free/RoHS Compliant) Package Options.

Diagrams