XC3S5000-5FGG676C

Product Summary

The XC3S5000-5FGG676C is a Spartan-3 Field-Programmable Gate Array. The device is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates. The XC3S5000-5FGG676C builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art Virtex-II tech-nology.

Parametrics

XC3S5000-5FGG676C absolute maximum ratings: (1)Internal supply voltage, VCCINT: -0.5 to 1.32 V; (2)Auxiliary supply voltage, VCCAUX: -0.5 to 3.00 V; (3)Output driver supply voltage, VCCO: -0.5 to 3.75 V; (4)Input reference voltage, VREF: -0.5 to VCCO +0.5 V; (5)Voltage applied to all User I/O pins and Dual-Purpose pins, VIN: 0.5 to VCCO +0.5 V; Voltage applied to all Dedicated pins, VIN: -0.5 to VCCAUX +0.5 V; (6)Junction temperature, VCCO < 3.0V, TJ: -125℃; VCCO > 3.0V, TJ: -105℃; (7)Soldering temperature, TSOL: -220℃; (8)Storage temperature, TSTG: -65 to 150℃.

Features

XC3S5000-5FGG676C features: (1)Revolutionary 90-nanometer process technology; (2)Very low cost, high-performance logic solution for high-volume, consumer-oriented applications; Densities as high as 74,880 logic cells; 326 MHz system clock rate; Three power rails: for core (1.2V), I/Os (1.2V to 3.3V), and auxiliary purposes (2.5V); (3)SelectIO signaling, Up to 784 I/O pins; 622 Mb/s data transfer rate per I/O; Seventeen single-ended signal standards; Seven differential signal standards including LVDS; Termination by Digitally Controlled Impedance; Signal swing ranging from 1.14V to 3.45V; Double Data Rate (DDR) support; (4)Logic resources, Abundant logic cells with shift register capability; Wide multiplexers; Fast look-ahead carry logic; Dedicated 18 x 18 multipliers; JTAG logic compatible with IEEE 1149.1/1532 ; (5)specifications, SelectRAM hierarchical memory; Up to 1,872 Kbits of total block RAM; Up to 520 Kbits of total distributed RAM; (6)Digital Clock Manager (up to four DCMs), Clock skew elimination; Frequency synthesis; High resolution phase shifting; (7)Eight global clock lines and abundant routing; (8)Fully supported by Xilinx ISE development system, Synthesis, mapping, placement and routing; (9)MicroBlaze processor, PCI, and other cores.

Diagrams